Cloud-based RTL tool for embedded RISC-V cores

August 07, 2020 //By Nick Flaherty
Codasip has added a cloud-based RTL simulator from Metrics Design Automation to its SweRV support package for the latest RISC-V embedded processor cores from Western Digital.
Codasip has added a cloud-based RTL simulator from Metrics Design Automation to its SweRV support package for the latest open source RISC-V embedded processor cores from Western Digital.

Western Digital is not a name you expect to be supplying open source processor cores. But its SweRV cores, based on the RISC-V open source architecture, are aimed at deeply embedded system-on-chip applications.

The SweRV cores available through another RISC-V core supplier, Czech processor tool designer Codasip, which has its own customisable RISC-V cores. Codasip has just done a deal to use the cloud-based SystemVerilog RTL Simulation Platform from Metrics Design Automation with SweRV support package.

The integration provides a very easy-to-use and inexpensive way for ASIC designers to verify modifications and enhancements they make to the SweRV embedded processor IP. The latest EH2 and EL2 32bit SweRV cores developed by Western Digital (WD) were added to the SweRV Support Package in June alongside the EH1 core.

The cloud-based simulation tool is the only RTL simulator available with a SaaS business model—users simply pay for use as a service. The implementation of Metrics simulator in the Cloud provides massive scalability so regression tests can run in parallel to complete in hours, not days.

“Western Digital do a lot of inhouse design for their storage products so you don’t get to see a lot about the designs but they have a lot of expertise in the processor areas. They embraced RISC-V early on and made a very significant commitment to it and invested in the Codasip series A funding,” said Roddy Urquhart, senior marketing director at Codasip.

​“In terms of RISC-Vs strategy they wanted to open source some of the technology. In December of last year they had been discussing how best to get their three high performance embedded cores to market. RTL on its own is not sufficient to deploy a core in an SoC,” he said.

Next: RISC-V SweRV support package 

Picture: 
The SystemVerilog RTL Simulation Platform from Metrics Design Automation

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